The only platform to master VLSI Design — from logic gates to SPI controllers
with real Verilator simulation, interactive waveforms, and hands-on challenges.
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Modules
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Levels
Real
Verilator Sim
Curriculum
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📚 Theory
Consoleidle
⏱ Waveform
Scroll to zoom · Hover to inspect signals
⚙ Verilator Options
Timing Mode
Warnings
Optimization
Language & Features
UVM — Universal Verification Methodology
⚠ UVM library not detected on this server
Your testbench must import uvm_pkg::*; and `include "uvm_macros.svh". Use run_test(); to launch the test.