From logic gates to SPI controllers — learn hardware description language
with real iverilog simulation, interactive waveforms, and hands-on challenges.
0
Lessons
6
Modules
3
Levels
Real
iverilog Sim
Curriculum
Pick a module to begin. Progress is saved automatically.
📚 Theory
Consoleidle
⏱ Waveform
Scroll to zoom · Hover to inspect signals
⚙ Verilator Options
Timing Mode
Warnings
Optimization
Language & Features
UVM — Universal Verification Methodology
⚠ UVM library not detected on this server
Your testbench must import uvm_pkg::*; and `include "uvm_macros.svh". Use run_test(); to launch the test.